Going Vertical: How 3D DRAM Could Change The Semiconductor Industry

Thursday - September 14 2023, 12:05 UTC - 1 year ago

Lam Research's engineers are creating proposals for 3D DRAM architecture that seek to shrink the nanosheets' footprints. They plan to make use of gate-all-around transistors and 24-layer tall stack of bitline layers. To make the capacitors more efficient, Lam Research is using Through-Silicon-Via (TSV) technology and plan to reduce the nanosheet's size with a "via array".

They expect the semiconductor industry to evolve from 2D to 3D DRAM over the next five to eight years based on current technical capabilities. Next generation memory is starting today with planning and architectural design.

Lam Research is simulating DRAM’s untested future by creating proposals for what 3D DRAM architecture could look like. They are using SEMulator3D® computer software, which is typically used to virtually fabricate devices by mimicking wafer fabrication. Here are some suggestions for a 3D DRAM architecture, addressing: • Scaling issues• Stacking challenges • Shrinking footprints • Innovative connections • Via arrays • Process requirements .

The plans is to till halve the volume needed for computer memory every 6-7 years.Today (D1z on the chart above), the area per bit is at about 20.4E-4 µm2. Soon, driving higher density of bits (i.e., further reduction of the area per bit) by reducing the footprint of the capacitors by making them taller will not be possible because etch and deposition processes for capacitor fabrication cannot handle the extreme (high) aspect ratio.

On the chart above, our industry is expected to be able to maintain 2D DRAM until reaching ~10.4E-4 µm2 area per bit, which is about five years out. After that the lack of space becomes a problem that will likely demand going vertical—3D DRAM.

Reimagined Architecture .

Lam Research’s designers using Lam’s SEMulator3D have proposed several changes to provide more space for capacitor processing while reducing the silicon area, thereby shrinking the nanosheets’ footprint.They moved the bitline (BL) to the opposite side of the nanosheet, so the current will travel through the entire nanosheet through the transistor gate. The effect overall increases space for capacitor processing and also reduces the silicon area’s footprint. A DRAM structure is composed of a conductive material/structure called a bitline, which provides the carriers (current) to be injected into a transistor.

Second, they introduced gate-all-around transistors to further reduce the silicon active area. They also made the capacitors—once skinny and tall—short and wide. This is possible because of the space gained by moving the BL to the center of the architecture.Finally, they increased the quantity of transistors/capacitors per bitline contact (no reason to be limited to two transistors per bitline) by placing transistors/capacitors on both sides of the bitline contact. This reconfigured nanosheet (as seen from a top-down view above) can then be stacked (as seen below). The first iteration of a stacked 3D DRAM would be 28 layers tall (above) and would be two nodes (~13E-4 µm2 per bit) ahead of D1z today. The more layers, of course, the more bits we have and therefore, the greater the density.

The key components of a 28-layer 3D nanosheet include: • A stack of gate-all-around nanosheet silicon transistors • A stack of bitline layers in between two rows of transistors • 24 vertical wordlines • Multibridge connections between bitline layers and transistors; transistors and capacitors • An array of horizontal MIM (metal-isolation-mental) capacitors .

Making the Via Array .

To avoid the limitation of downscaling the capacitor, the team decided to utilize Lam Research’s latest Through-Silicon-Via (TSV) technology. This will reduce the nanosheet’s size by “swapping” the 6 transistors and capacitors per bitline (at the nanosheet level) for “via array”.The full via array provides the same function as 6 transistors and capacitors per bitline with only one TSV, thereby reducing the design down to one transistor per bitline contact.